Method and device for improved magnetic field generation during a write operation of a magnetoresistive memory device

ABSTRACT

The present invention relates to magnetic or magnetoresistive random access memories (MRAMs), and more particularly to a method and a device for modulating a generated magnetic field during a write operation of such a magnetoresistive memory device. The present invention provides a matrix ( 30 ) with magnetoresistive memory cells ( 31 ) logically organized in rows and columns, each memory cell ( 31 ) including a magnetoresistive element ( 32 ). The matrix ( 30 ) comprises a set of row lines ( 33 ), a row line being a continuous conductive strip which is magnetically couplable to the magnetoresistive element ( 32 ) of each of the memory cells ( 31 ) of a row. The matrix ( 30 ) also comprises a set of column lines ( 34 ), a column line ( 34 ) being a continuous conductive strip which is magnetically couplable to the magnetoresistive element ( 32 ) of each of the memory cells ( 31 ) of a column, wherein for each column line ( 34 ) at least one return column line ( 35 ) is provided for forming a return path for current in that column line ( 34 ) and for adding to a magnetic field influencing a selected magnetoresistive element ( 32 ) and generated by current flow in the column line ( 34 ) for increasing the magnetic field for writing to the selected magnetoresistive element ( 32 ).

The present invention relates to magnetic or magnetoresistive randomaccess memories (MRAMs), and more particularly to a method and a devicefor modulating a generated magnetic field during a write operation ofsuch a magnetoresistive memory device.

Magnetic or Magnetoresistive Random Access Memory (MRAM) is currentlybeing considered by many companies as a successor to flash memory. Ithas the potential to replace all but the fastest static RAM (SRAM)memories. It is a non-volatile memory device, which means that no poweris required to sustain the stored information. This is seen as anadvantage over most other types of memory.

The MRAM concept was originally developed at Honeywell Corp. USA, anduses magnetization direction in a magnetic multilayer device asinformation storage and the resultant resistance difference forinformation readout. As with all memory devices, each cell in an MRAMarray must be able to store at least two states which represent either a“1” or a “0”.

Different kinds of magnetoresistive (MR) effects exist, of which theGiant Magneto-Resistance (GMR) and Tunnel Magneto-Resistance (TMR) arecurrently the most important ones. The GMR effect and the TMR orMagnetic Tunnel Junction (MTJ) or Spin Dependent Tunneling (SDT) effectprovide possibilities to realize a.o. non-volatile magnetic memories.These devices comprise a stack of thin films of which at least two areferromagnetic or ferrimagnetic, and which are separated by anon-magnetic interlayer. GMR is the magneto-resistance for structureswith conductor interlayers and TMR is the magneto-resistance forstructures with dielectric interlayers. If a very thin conductor isplaced between two ferromagnetic or fernmagnetic films, then theeffective in-plane resistance of the composite multilayer structure issmallest when the magnetization directions of the films are parallel andlargest when the magnetization directions of the films areanti-parallel. If a thin dielectric interlayer is placed between twoferromagnetic or ferrimagnetic films, tunneling current between thefilms is observed to be the largest (or thus resistance to be thesmallest) when the magnetization directions of the films are paralleland tunneling current between the films is the smallest (or thusresistance the largest) when the magnetization directions of the filmsare anti-parallel.

Magneto-resistance is usually measured as the percentage increase inresistance of the above structures going from parallel to anti-parallelmagnetization states. TMR devices provide higher percentagemagneto-resistance than GMR structures, and thus have the potential forhigher signals and higher speed. Recent results indicate tunnelinggiving over 40% magneto-resistance, compared to 6-9% magneto-resistancein good GMR cells.

An MRAM comprises a plurality of magnetoresistive memory units 1arranged in an array. One such prior art memory unit 1 is shown inFIG. 1. Each memory unit 1 comprises a magnetoresistive memory element2, a first intersection of a digit line 4 and a bit line 6, and a secondintersection of the bit line 6 and a word line 8. The memory units 1 arecoupled in series in columns by means of the bit lines 6 and coupled inseries in rows by means of the digit lines 4 and word lines 8, thusforming the array. The magnetoresistive memory elements 2 used may forexample, but not limited thereto, be magnetic tunnel junctions (MTJs).

MTJ memory elements 2 generally include, as shown in FIG. 2, a layeredstructure comprising a fixed or pinned layer 10, a free layer 12 and adielectric barrier 14 in between. The MTJ memory element 2 furthermorecomprises a non-magnetic conductor forming a lower electrical contact22, and an upper contact 16 on e.g. the free magnetic layer 12. Thestack of free and pinned layers can also be reversed, so that the uppercontact is on the pinned magnetic layer. The pinned magnetic layer 10and the free magnetic layer 12 may both be composed of e.g. NiFe, andthe dielectric barrier layer 14 may e.g. be made of AlOx. Moreover bothfree and pinned layers can be formed by a multilayer of differentmagnetic layers, also in combination with non-magnetic orantiferromagnetic layers. By applying a small voltage over the sandwichof ferromagnetic or ferrimagnetic layers 10, 12 with the dielectric 14therebetween, electrons can tunnel through the dielectric barrier 14.

The pinned layer 10 of magnetic material has a magnetic vector thatalways points in the same direction. The magnetic vector of the freelayer 12 is free, but constrained by the physical size of the layer, topoint in either of two directions: parallel or anti-parallel with themagnetization direction of the pinned layer 10.

An MTJ memory element 2 is used by connecting it in a circuit such thatelectricity can flow vertically through the element 2 from one of themagnetic layers to the other. The MTJ unit 1 can be electricallyrepresented by a resistor R in series with a switching element such as atransistor T, as shown in FIG. 1. The size of the resistance of theresistor R depends on the orientation of the magnetic vectors of thefree and pinned magnetic layers of the memory element 2. The MTJ element2 has a relatively high resistance (HiRes) when the magnetic vectorspoint in opposite directions, and it has a relatively low resistance(LoRes) when the magnetic vectors point in the same direction.

A diagrammatic elevational view of a 2×2 array of prior art memory unitsis shown in FIG. 2. In an MRAM array, comprising a plurality of MRAMunits, orthogonal conductive lines 4, 6 pass under and over each bit ormemory element 2, carrying current that produces a switching field. Eachbit is designed so that it will not switch when current is applied tojust one line, but will switch when current is flowing through bothlines 4, 6 that cross at the selected bit (switching will occur only ifthe magnetic vector of the free layer is not in accordance with thedirection of the switching field).

Digit lines 4 and bit lines 6 are provided in an array of MTJ memoryunits 1, where the digit lines 4 travel along the rows of the array onone side of the memory elements 2, and the bit lines 6 travel down thecolumns of the array on the opposite side of the memory elements 2. Thestructure in FIG. 2 is partially inverted for clarity purposes: digitlines 4 physically run underneath the MTJ elements 2 (at that side ofthe MTJ elements 2 oriented towards the substrate in which thetransistor T is provided), and bit lines 6 physically run over the MTJelements 2 (at that side of the MTJ elements 2 oriented away from thesubstrate in which the transistor T is provided). However, if drawn thatway, the bit lines 6 would obscure the magnetoresistive elements 2,which are the more relevant parts of the drawing.

The memory element 2 is connected to the transistor T by means of aninterconnect layer 16 and a plurality of metalization layers 18 and vias20. There is a galvanic connection 22 between the memory element 2 andthe bit line 6. The transistor T of each memory unit 1 is connected to aground line 24.

In write or program mode, required currents flow through selected digitlines 4 and bit lines 6 so that at their intersection a peak magneticfield is generated, sufficient to switch the polarization of the freelayer 12 of the MTJ element 2, so as to switch the resistance of the MTJunit 2 from the LoRes (low resistance) state to the HiRes (highresistance) state or vice versa (depending on the direction of thecurrent through the bit line 6). At the same time, the switching elementsuch as transistor T in the selected memory unit 1 (the memory unit atthe intersection of the selected digit line 4 and the selected bit line6) is in the cut-off state, for example by keeping the voltage on theword line 8 low (0 volt in case the switching element is a transistorT). The currents in the selected digit line 4 and the selected bit line6 are such that together they provide a magnetic field able to changethe direction of the magnetic vector of the free layer of the selectedmemory element, but the current in either strip by itself is not able tochange the storage state. Therefore only the selected memory element iswritten, not any of the other memory elements on the same selected digitline 4 or bit line 6.

A disadvantage with MRAM is that the programming current needed is veryhigh, because of the requirement of two high enough magnetic fieldsbeing induced in the neighborhood of the magnetoresistive material. Indemos by IBM and Motorola, 0.6 μm CMOS technology proves to give stableread and write operations using currents in the 5 to 10 mA range.Typical devices in these demonstrations were about 0.1 to 0.5 μm².

Scaling of RAM technology into the sub-100 nm area is desirable in orderto get smaller memories, but it is not straightforward. Magneticelements typically have some aspect ratio to stabilize favorablemagnetization directions by shape anisotropy. However, smallerdimensions lead to increasing switching fields for a fixed aspect ratio.Therefore, the aspect ratio should be reduced for smaller devices. Onthe other hand, long-term thermal stability, i.e. data retention,requires a certain minimal energy barrier (K_(u)V) against switching,which is basically setting a minimum value for the switching field(˜K_(u)).

Magnetic fields are created on-chip by sending a current through bit orword lines, in general called current lines, and are proportional to thecurrent. For obtaining higher magnetic fields, higher currents need tobe used. However, low power applications will require low currents.Those are contradictory requirements. Scaling laws are also applied tothe current lines, in particular to their cross-section. The currentdensity in a current line is limited to ˜10⁷ A/cm², a typicalelectromigration limit for Cu. At higher current densities, metal atomsmigrate in the current line, resulting in a break in the metal line. Theabove-mentioned limit sets an upper limit to the current in a Cu currentline to 1 mA per 100 nm×100 nm section. In other words, the magneticfield amplitude which can be generated when scaling down prior artmagnetoresistive memory devices is limited.

U.S. Pat. No. 6,385,083 allegedly solves this problem by providing, foreach memory element, a bit line and a plurality of word lines. Currentsthrough these lines all contribute to the magnetic field for a selectedmemory cell. By this solution, for a same conductor or current line sizeand current density, significantly higher write fields (magnetic fields)are obtained. In the alternative, for a same write field, currentdensity in the write lines can be decreased, which reduceselectromigration problems. However, each of the word lines is driven bya row driver, and therefore the total power consumption is increased,which is undesirable in low power applications.

It is an object of the present invention to improve magnetic fieldgeneration in a magnetic memory.

For example, improved magnetic field generation may include: generatinga higher magnetic field for a given current density and/or decreasingcross-talk to neighboring, non-selected memory cells, and/or creating abetter uniformity of the magnetic field throughout the memory device.

The above objective is accomplished by a device and method according tothe present invention.

For a fixed technology, i.e. the geometry of current lines and storageelements is fixed, it is proposed to use “active write field shaping” bycreating at least one particular magnetic field component from currentsin multiple current lines, rather than only one current line, whereinthe multiple current lines comprise at least a normal current line and acurrent line functioning as a return path for the current. With “activewrite field shaping” is meant that the magnetic field profile can belocally changed, or shaped, by addition of magnetic field profiles frommultiple current lines. Active write field shaping may therefore bedescribed as multi-source magnetic field generation. According to thepresent invention, the field created from the return path is used toincrease the magnetic field and/or reduce cross-talk. As the currentline functioning as a return path adds to generate a magnetic fieldcomponent in a selected memory element, it is called a “functionalreturn path” in the current disclosure.

The present invention provides a matrix with magnetoresistive memorycells logically organized in rows and columns, each memory cellincluding a magnetoresistive element. The matrix comprises a set ofcolumn lines, a column line being a continuous conductive strip which ismagnetically couplable to the magnetoresistive element of each of thememory cells of a column, wherein for each column line, at least onereturn column line is provided for forming a return path for current inthat column line and for adding to a magnetic field influencing aselected magnetoresistive element and generated by current flow in thecolumn line for increasing the magnetic field for writing to theselected magnetoresistive element. The matrix may further comprise a setof row lines, a row line being a continuous conductive strip which ismagnetically couplable to the magnetoresistive element of each of thememory cells of a row. A combined magnetic field generated by currentthrough a row line corresponding to a selected memory cell, by currentthrough a column line corresponding to the selected memory cell, and bycurrent through the corresponding return column line is sufficientlyhigh for switching (dependent on the content of the memory cell) themagnetic status of the magnetoresistive element of the selected memorycell. A magnetic field generated by current through any of the namedcurrent lines is not high enough to provide a switching field. It is anadvantage of the present invention that lower current levels can be sentthrough the row line, column line and return line, while still aswitching field is generated. The matrix according to the presentinvention allows realization of higher magnetic fields at maximumcurrent density, which allows postponement of the fundamental thermalstability limit when scaling to smaller dimensions. Advantages includeat least one of low power, possibility to reduce cross-talk inneighboring elements, possibility to improve magnetic field amplitudethroughout the magnetic storage element.

The present invention is described with a column line having a returnline, but “row lines” and “column lines” are names given for ease ofreference only, and may be, but do not necessarily refer to the physicalorientation of those lines.

In one embodiment, a return column line may be one of the other columnlines. This has the advantage that no separate current lines need to beprovided.

In another embodiment, the return column lines are different from thecolumn lines. This means that separate current lines need to beprovided, but it has the advantage that parallel writing to a pluralityof columns is possible. For each column line, a return column line maybe provided at opposite sides of a column of magnetoresistive elements.

According to one embodiment, the column of magnetoresistive elements maybe placed offset in a row-direction with regard to the center of thecolumn lines. According to another embodiment, the column ofmagnetoresistive elements may be placed offset in a row-direction withregard to the center of the return column lines. According to yetanother embodiment, the column of magnetoresistive elements may beplaced symmetrically with regard to both the column line and at leastone return column line. These different configurations all lead todifferent maximum obtainable magnetic fields, different powerconsumption and different power efficiency.

The present invention also provides that not only each column line isprovided with at least one return column line, but that also each rowline is provided with at least one return row line for forming a returnpath for current in that row line and for adding to the magnetic fieldof a selected magnetoresistive element.

According to yet another embodiment of the present invention, the columnlines and/or the return column lines and/or the row lines and/or thereturn row lines are provided with a flux guiding cladding layer. Anadvantage of such cladding layer is that the magnetic fields in therespective layers are more concentrated, and that cross-talk is reduced,hence unwanted programming is avoided.

The present invention also provides a nonvolatile memory comprising amatrix with magnetoresistive memory cells according to any of theprevious claims. This memory may be a memory with multiple banks ormodules. Such nonvolatile memory may be used e.g. in microprocessors, incomputers, in mobile telephones, in printers, in microcontrollers, as amemory in smartcards, or for any other suitable application. Suchnonvolatile memory may also replace optical storage. The data is storedin the MRAM, and reading occurs with a special designated magneticreading head.

The present invention furthermore provides a method of writing amagnetoresistive element in a matrix of magnetoresistive memory elementsarranged in logically organized rows and columns. The method comprisescombining, in the magnetoresistive element, a magnetic field from acurrent line with a magnetic field from at least one return current lineto thereby increase the magnetic field for writing to themagnetoresistive element. An advantage of the method of the presentinvention is that lower currents can be sent in the current lines toobtain a magnetic field sufficient to write a value in amagnetoresistive element. The total magnetic field from at least threedifferent current lines is used, of which at least two, forming one ofthe magnetic field components, are sharing the same current source, i.e.so that one forms a current path and the other forms a return currentpath.

Due to the fact that a current path and a return current path areprovided, only single-polarity current sources are needed for row and/orcolumn drivers.

These and other characteristics, features and advantages of the presentinvention will become apparent from the following detailed description,taken in conjunction with the accompanying drawings, which illustrate,by way of example, the principles of the invention. This description isgiven for the sake of example only, without limiting the scope of theinvention. The reference figures quoted below refer to the attacheddrawings.

FIG. 1 is an electrical representation of an MRAM unit for connection inan array according to the prior art.

FIG. 2 is a diagrammatic elevational view of a 2×2 array of MTJ unitsaccording to the prior art.

FIG. 3 is a schematic illustration of an MRAM architecture with a memoryarray, a single current source/sink unit for one of the magnetic fieldcomponents, and a current return path according to a first embodiment ofthe present invention.

FIG. 4 is a schematic cross-section of part of the memory array of FIG.3.

FIG. 5 is a schematic explanation of the creation of different currentpaths.

FIG. 6 illustrates write field gain for different embodiments having thesame power efficiency.

FIG. 7 illustrates a functional current return path according to asecond embodiment of the present invention.

FIG. 8 is a schematic diagram of an MRAM architecture according to thepresent invention for word-parallel write operations.

FIG. 9 is a schematic diagram of a further embodiment of the presentinvention with a single current source for simultaneously providing anequally distributed current to different bits in a word.

FIG. 10 schematically illustrates a serial single current sourceword-parallel MRAM.

FIG. 11 illustrates different embodiments ((b) to (e)) of active fieldshaping according to the present invention, compared to the prior artsituation (a).

FIG. 12 is a graph of the calculated magnetic fields for the differentembodiments of FIG. 11.

FIG. 13 is a graph of a normalized field uniformity throughout thetunnel junction for the different embodiments of FIG. 11.

FIG. 14 illustrates different layouts of embodiments of current lineshaving functional return lines.

In the different figures, the same reference figures refer to the sameor analogous elements.

The present invention will be described with respect to particularembodiments and with reference to certain drawings but the invention isnot limited thereto but only by the claims. The drawings described areonly schematic and are non-limiting. In the drawings, the size of someof the elements may be exaggerated and not drawn on scale forillustrative purposes. Where the term “comprising” is used in thepresent description and claims, it does not exclude other elements orsteps. Where an indefinite or definite article is used when referring toa singular noun e.g. “a” or “an”, “the”, this includes a plural of thatnoun unless something else is specifically stated.

The terms first, second, third and the like in the description and inthe claims, are used for distinguishing between similar elements and notnecessarily for describing a sequential or chronological order. It is tobe understood that the terms so used are interchangeable underappropriate circumstances and that the embodiments of the inventiondescribed herein are capable of operation in other sequences thandescribed or illustrated herein.

Moreover, the terms top, bottom, over, under and the like in thedescription and the claims are used for descriptive purposes and notnecessarily for describing relative positions. It is to be understoodthat the terms so used are interchangeable under appropriatecircumstances and that the embodiments of the invention described hereinare capable of operation in other orientations than described orillustrated herein.

According to the present invention, a matrix 30 of magnetoresistivememory cells 31, each memory cell 31 comprising a magnetoresistivememory element 32, is logically organized in rows and columns.Throughout this description, the terms “horizontal” and “vertical” areused to provide a co-ordinate system and for ease of explanation only.They do not need to, but may, refer to an actual physical direction ofthe device. Furthermore, the terms “column” and “row” are used todescribe sets of array elements which are linked together. The linkingcan be in the form of a Cartesian array of rows and columns however thepresent invention is not limited thereto. As will be understood by thoseskilled in the art, columns and rows can be easily interchanged and itis intended in this disclosure that these terms be interchangeable.Also, non-Cartesian arrays may be constructed and are included withinthe scope of the invention. Accordingly the terms “row” and “column”should be interpreted widely. To facilitate in this wide interpretation,the claims refer to logically organized rows and columns. By this ismeant that sets of memory elements are linked together in atopologically linear intersecting manner however, that the physical ortopographical arrangement need not be so. For example, the rows may becircles and the columns radii of these circles and the circles and radiiare described in this invention as “logically organized” in rows andcolumns. Also, specific names of the various lines, e.g. bitline andwordline, or row line and column line, are intended to be generic namesused to facilitate the explanation and to refer to a particular functionand this specific choice of words is not intended to in any way limitthe invention. It should be understood that all these terms are usedonly to facilitate a better understanding of the specific structurebeing described, and are in no way intended to limit the invention.

FIG. 3 is a diagrammatic illustration of a top view of an MRAM device40, such as for example an MRAM array, a memory module, a memory bank ora memory consisting of several memory banks, according to a firstembodiment of the present invention, comprising an array or matrix 30 ofmagnetoresistive memory elements 32, such as e.g. GMR or MTJ elements.The matrix 30 is provided with row lines 33 and column lines 34. A rowline 33 is a continuous conductive strip, e.g. a copper line, which ismagnetically couplable to the magnetoresistive elements 32 of a row ofthe matrix 30. A row line extends in a first direction. A column line 34is a continuous conductive strip, e.g. a copper line, which ismagnetically couplable to the magnetoresistive elements 32 of a columnof the matrix 30. A column line 34 extends in a second direction. In theembodiment described, the second direction is perpendicular to the firstdirection. This, however, is an example only and is not limiting. Foreach column line 34, at least one corresponding return column line 35 isprovided. This return column line 35 forms a functional return path forthe current in the corresponding column line 34, i.e. the current from acolumn current source 36 through an appropriate column line 34 generatesa first magnetic field in a selected magnetoresistive element 32 (aswell as in all other magnetoresistive elements 32 of that column). Thiscurrent is returned to a column current sink, which in the embodimentshown is physically the same element as the current source 36, throughthe at least one corresponding return column line 35, thus generating asecond magnetic field in the selected magnetoresistive element 32 (aswell as in all other magnetoresistive elements 32 of that column).According to another embodiment of the present invention (notrepresented in the drawings), it is also possible to provide separatecurrent source and current sink devices. Furthermore, a current from arow current source 37 is sent through an appropriate row line 33 to arow current sink 38, thus generating a third magnetic field in theselected magnetoresistive element 32 (as well as in all othermagnetoresistive elements 32 of that row). The combination of the first,second and third magnetic fields in the selected magnetoresistiveelement 32 provides a magnetic field able to change the direction of themagnetic vector of the free layer of this element 32, but either of themagnetic fields by itself or a combination of not all those magneticfields, is not able to change the storage state. Therefore only theselected memory cell 31 is written. A power supply 39 provides thenecessary power for generating the row currents and the column currents.Only a limited number of memory cells 31 are shown in FIG. 3, but inpractice the memory array 30 can be of any size.

Reference is made to FIG. 4, which illustrates a cross-sectional view ofthe matrix 30 of FIG. 3, including an array of magnetoresistive memorycells 31, each memory cell 31 comprising a magnetoresistive memoryelement 32. The magnetoresistive memory elements 32 may includemagnetoresistive devices such as tunneling magnetoresistive (TMR)devices or giant magnetoresistive (GMR) devices. The magnetoresistivememory cells 31 are arranged in rows and columns.

Row lines 33 extend in the first direction in a plane on one side of thearray 30 of memory cells 31, for example on the top thereof. Columnlines 34 extend in the second direction in a plane on the opposite sideof the array 30 of memory cells 31, in the example given at the bottomside thereof. Furthermore, return path lines 35 are provided, extendingin the second direction in a plane at the same side of the array ofmemory cells 31 as the row lines 33, i.e. in the example give on the topof the array 30. As the return current path forms a closed loop, asingle current source/sink element 36 may be provided on one side of thememory matrix 30. By directing the current into the upper or lowerconductor 34, 35 of the loop, a unipolar current source 36 can beutilized in combination with a couple of switches 50, 51 such as e.g.semiconductor switches, as shown in FIG. 5. FIG. 5 further clarifies thecombination of switches 50, 51 to be selected in order to createdifferent current source-to-sink paths for writing logical 0 (left-handside of FIG. 5) and 1 (right-hand side of FIG. 5) values. Arrows forcurrent path and closed switches are added for clarity.

If a first binary value, e.g. a 0-value, is to be written in memoryelement 32 of magnetoresistive memory cell 31A (selected cell), then theswitches 50 are closed, while switches 51 are opened. For claritypurposes only, row lines 33 are omitted FIG. 5. However for switching acurrent must be present in the row line crossing memory cell 31 A.Current coming from current source 36 is directed through a first switch50, through a first column line 52 over the selected memory cell 31A,through a second column line 53 underneath the selected memory cell 31A,and back to a column current sink. This column current sink may or maynot physically be the same element as column current source 36. Thesecond column line 53 is a return column line. If a second binary value,e.g. a 1-value, is to be written in memory element 32 ofmagnetoresistive memory cell 31A (selected cell), then the switches 51are closed, while switches 50 are opened. Current coming from currentsource 36 is directed through a first switch 51, through the secondcolumn line 53 underneath the selected memory cell 31A, through thefirst column line 53 above the selected memory cell 31A, and back to thecolumn current sink. The column current sink may or may not physicallybe the same element as column current source 36. The first column line53 now functions as a return column line. When thus changing thedirection of the current through the first and second column lines 52,53 by appropriately switching the switches 50, 51, the generatedmagnetic field in memory cell 31A switches direction, as represented byarrow 54 in FIG. 5.

In FIG. 6, a comparison of different situations is made. Part (a) ofFIG. 6 represents a prior art situation, in which only one column line34 is provided for each memory element 32. When the resistance of thecurrent line 34 is fixed, e.g. R, it requires R. I² to generate a fieldH in the memory element 32 of the prior art configuration, i.e. in amemory cell 31 with no current return path line provided for adding ingenerating a magnetic field in the memory element 32. If powerefficiency is defined as the ratio between the power consumption togenerate a magnetic field, and the generated magnetic field itself, thepower efficiency for this prior art situation is (R.I²) /H. In order todouble the magnetic field value, either of two options can be chosen.According to the prior art, the magnetic field value would be doubled bydoubling the current in the column line 34, as shown in part (b) of FIG.6. The power needed to generate the magnetic field 2H is then R. (2I)²,and the power efficiency is (R. (2I)²)/(2H), or thus (2. R. I²)/H.According to the present invention, however, a current I is sent throughthe column line 34, and a corresponding return current is sent through areturn path line 35. The power needed to generate the magnetic field 2His for this embodiment (R. I²+R. I²), and the power efficiency is (R.I²+R. I²)/(2H), or thus (R. I²)/H. This means that by using a functionalreturn path 35 according to the present invention, i.e. a return pathwhich substantially contributes to the generation of a magnetic field ina selected memory cell, magnetic fields generated in the magnetic memorycells 31 are doubled for a same power consumption.

According to a further embodiment of the present invention, flux guidingcladding layers 60 (part (d) of FIG. 6) may be provided at the columnlines 34, at the return path lines 35 and/or at the row lines 33. Theseflux guiding cladding layers 60 are of a high permeability andmagnetically soft (low coercivity), such as e.g. nickel iron (NiFe).These flux guide cladding layers 60 lead to a better localization of themagnetic field into the area of the selected cell. A gain of factor 2 infield magnitude can be realized this way. Moreover, the selectivity toneighboring memory elements 32 is enhanced, and thus cross-talk inneighboring memory elements 32 is reduced by using such flux guidingcladding layers 60. The flux guiding cladding layer 60 may cover onlyone side of a row line 33, column line 34, and/or return path line 35,preferably the side away from the memory element 32, or it may cover upto three sides thereof (as shown in part (d) of FIG. 6) for maximumefficiency.

According to a further embodiment of the present invention, a current issent through a selected column line 34, and returned to the two adjacentcolumn lines 70, 71 (one at either side of column line 34), and a partthrough each of the adjacent column lines 70, 71, e.g. one half of thecurrent through each of those adjacent column lines 70, 71. By adding aconnection scheme, as represented in FIG. 5, at the end of the matrix 30where the current source 36 is not provided, bipolar return currentpaths can easily be formed, and a bit-serial write operation can beperformed. By doing this, for an ultra-high density pacling, theeffective magnetic field at neighboring elements is reduced. The powerconsumption is (R. (I/2)²+R. I²+R.(I/2)²), or thus 3/2. R. I². Thismeans that the effective power consumption of this embodiment isincreased with 50% with regard to the prior art embodiment as depictedin part (a) of FIG. 6. However, cross-talk is reduced, roughly by afactor 2. The maximum magnetic field in the selected memory cell isslightly reduced.

Different bit-specific current source/sink units according to any of theembodiments of the present invention can be combined into a largerentity for word-parallel writing. This is schematically represented inFIG. 8. The current driver is then simply responding to the data to bewritten in the following way. In e.g. an 8-bit version, upon receipt ofthe word 10010110, the switches 50, 51 are closed for the sequence ofbits in an appropriate way so as to be able to write the sequence1-0-0-1-0-1-1-0 in subsequent bits. It is to be noticed that everycolumn of bits requires four switches in this scheme, hence two switchesare selected for each bit value in the word.

Power consumption, peak current and write time are analyzed for thisarchitecture.

If the return path would not contribute to the magnetic field, but wouldsimply double the resistance of the current line with respect to theconventional case, then it is found that for a 1-cycle write operationthat the power consumption equalsn.(2R).I ² +R.I ²=(2n+1).R.I ².The first term, n.(2R).I², is the power dissipated by the column linesand their return paths; the second term, R.I², is the power dissipatedby the row line (for clarity purposes not represented in FIG. 8)corresponding to the bits to be written. The power consumption in thiscase is thus higher than for the conventional case. The peak current is(n+1).I.A multi-phase clock system can be implemented, as disclosed in U.S. Pat.No. 6,236,611, reducing the peak current to 2I, but the powerconsumption is nown((2R).I ² +R.I ²)=n.3.R.I ².

As explained before, according to the present invention only half of thecurrent is needed in the current loop to achieve the same magnetic fieldvalue, since the return path participates equally in the fieldgeneration. However, the current line resistance is doubled, as itslength is. In a 1-cycle write operation, the power consumption nowequals${{n \cdot ( {2R} ) \cdot ( \frac{I}{2} )^{2}} + {R \cdot I^{2}}} = {( {\frac{n}{2} + 1} ) \cdot R \cdot {I^{2}.}}$As could be expected, this value is roughly half compared tostate-of-the-art MRAM architectures. The peak current is now$( {\frac{n}{2} + 1} ) \cdot I$If a multi-phase clock is implemented, the peak current is reduced to$\frac{3}{2} \cdot I$per cycle. However, the total power consumption after n-cycles isincreased to${n \cdot ( {{( {2R} ) \cdot ( \frac{I}{2} )^{2}} + {R \cdot I^{2}}} )} = {n \cdot \frac{3}{2} \cdot R \cdot {I^{2}.}}$

Thus a return current path only leads to a reduction in powerconsumption if the ‘return’ current contributes to the magnetic fieldgeneration. The optimum will be at equal contribution of both currentcomponents. A break-even point with conventional technology is found for˜30% contribution of the return current path to the field generation. Inany other case, one has to make sure that the extra resistance caused bythe return path is kept minimal.

According to an embodiment of the present invention, making use of theintrinsic resistance equality in the different channels, a singlecurrent source (with level ˜n.I) may be used, rather than n differentsmaller current sources (level ˜I). The principle is sketched in FIG. 9.The decision about the ultimate implementation should be based on asmaller variation in the current line resistance values, rather than thedifferent current source levels. In other words, when the statisticalvariation in the resistance of the different current loops is verysmall, a single current source built around an enlarged-gate transistormay give a better control over the current levels in the differentloops.

The current source/sink unit may be improved in another manner. FIG. 10clearly shows the serial approach by feeding the current sink of thefirst bit into the current source of the second bit, etc. If each of theswitches 50, 51 are appropriately switched, the right content can bewritten for each of the bits, as shown in the bottom part of FIG. 10.Therefore, a smaller current source 36 proves to be adequate, thussaving substrate area, e.g. silicon area. However, the power consumptioncannot immediately be reduced due to the extended current line (factorn). For a 1-cycle write operation, a peak current of only 3/2.I isrequired. In this approach, the advantages of a smaller powerconsumption are combined with a fast write time and a low peak current.In a modular approach for MRAM, smaller memory banks or blocks may beused to reduce the overall current line resistance. This is typicallydone to reduce voltage losses over the current lines.

According to yet another embodiment of the present invention, a betteruniformity of the magnetic field throughout the memory element may becreated. The requirement of using minimal line width is relaxed in thisembodiment. Of course, such an implementation will lead to a loss ofdensity for MRAM arrays. However, it may be advantageous to trade offdensity for improved magnetic field uniformity.

Different situations, represented in parts (a) to (e) of FIG. 11 arecompared. Part (a) represents a single current line 34, according to theprior art. Part (b) represents a current line 34 with a return path 35above the magnetoresistive element 32 according to the first embodimentof the present invention described hereinabove. The magnetoresistiveelement 32, the current line 34 and the return path 35 all have the samewidth, and all elements 32, 34, 35 are placed symmetrically with respectto each other. Part (c) represents a current line 34 with a return path35, whereby both the current line 34 and the return path 35 are extendedto have a width which corresponds to 1.5 times the width of the memoryelement 32, and whereby the conductors 34, 35 are offset with regard tothe memory element 32. Part (d) is as part (c), but whereby theconductors 34, 35 are extended so as to have a width, which is twice thewidth of the memory element 32. Part (e) is as part (d), but whereby theconductors 34, 35 are placed symmetrically with respect to themagnetoresistive element 32. Table 1 gives an overview of the inputparameters in the calculation for both lines. These values are takenfrom a typical CMOS090 process flow. TABLE 1 Distance line to Width lineHeight line memory element (a) Bottom line 200 nm 325 nm 110 nm Top line/ / / (b) Bottom line 200 nm 325 nm 110 nm Top line 200 nm 250 nm 400 nm(c) Bottom line 300 nm 325 nm 110 nm Top line 300 nm 250 nm 400 nm (d)Bottom line 400 nm 325 nm 110 nm Top line 400 nm 250 nm 400 nm (e)Bottom line 400 nm 325 nm 110 nm Top line 400 nm 250 nm 400 nm

Table 2 gives an overview of calculated magnetic fields, powerconsumption, required currents, power efficiency, maximum current gainfactor and maximum possible magnetic field for the different embodimentsrepresented in FIG. 11. TABLE 2 (a) (b) (c) (d) (e) Magnetic field 0.7821.522 1.458 1.410 1.322 (kA/m/mA) Power R · I² 2 · R · I² 2 · (⅔ R) · I²2 · (½ R) · I² 2 · (½ R) · I² consumption Required 0.639 0.328 0.3430.355 0.378 current for generating H = 0.5 kA/m Power 0.817 0.430 0.3140.252 0.286 efficiency (R = 1) Power 100% 52.6% 38.4% 30.8% 35.0%consumption Prior art Max. current 1× 1× 1.5× 2× 2× gain factor Max.field for 0.782 1.522 2.187 2.820 2.644 I = 1 mA (kA/m)

The calculated magnetic field is represented in FIG. 12, in function ofdistance from the memory element. The letters associated with the graphsrefer to each of the cases represented in FIG. 11. Using the samecurrent in all situations, a small reduction in the magnetic field isobserved when using wider lines (embodiments (c), (d) and (e)). However,the power efficiency is much improved due to the reduced current lineresistance. Moreover, due to the larger cross-section, higher fields cannow be generated for constant current density. The power consumption canbe reduced with about a factor of at least two to three.

FIG. 13 illustrates enhanced field uniformity for wider current lines infunction of distance from the memory element. The letters associatedwith the graphs refer to each of the cases represented in FIG. 11. Forthe same current, asymmetrical current lines, i.e. embodiments (c) and(d) give rise to higher obtainable magnetic fields, in comparison to thesymmetrical embodiment (e). The gain in magnetic field for asymmetricalcurrent lines, however, is tampered by a small reduction in fielduniformity.

A few different layouts for a 0T-1MTJ MRAM device using active fieldshaping according to the present invention are shown in FIG. 14. Tominimize write fields, minimal dimensions (for a given technology, i.e.e.g. 200×100 nm² for CMOS090) are combined, for the memory elements 32,e.g. magnetic tunnel junctions, with a write line or column line 34 of400 nm rather than 200 nm for the vertical write lines. Differentimplementations of the horizontal write lines or row lines 33 can beenvisaged, as shown in FIG. 14.

In first instance, a prior art architecture is represented, a top viewin part (1 a) of FIG. 14 and a cross-section in part (1 b) thereof. Nofunctional current return paths are provided, for the column lines 34nor for the row lines 33.

The first embodiment of the present invention is also illustrated inparts (2 a) and (2 b) of FIG. 14, which are a top view and a verticalcross-sectional view of a device according to this embodiment,respectively. Double symmetrical return lines are provided, i.e. acolumn return line 35 is provided for each column line 34 and associatedtherewith and a row return line 80 is provided for each row line 33 anassociated therewith. A column line 34 and its associated column returnline 35 are placed symmetrically with respect to the memory element 32,and a row line 33 and its associated row return line 80 are also placedsymmetrically with respect to the memory element 32, as can be seen inthe cross-sectional view (2 b).

Another embodiment of the present invention is illustrated in parts (3a) and (3 b) of FIG. 14, which are a top view and a verticalcross-sectional view of a device according to this embodiment,respectively. Vertical asymmetrical return lines and horizontalsymmetrical return lines are provided, i.e. a column return line 35 isprovided for each column line 34 and associated therewith and a rowreturn line 80 is provided for each row line 33 an associated therewith.A column line 34 and its associated column return line 35 are placedasymmetrically with respect to the memory element 32, as can be seen inpart (3 b) of FIG. 14, i.e. there is an offset between column line 34and memory element 32 in the direction in which the row lines 33 extendand between return line 35 and memory element 32 in the direction inwhich the row lines 33 extend. In this embodiment, a row line 33 and itsassociated row return line 80 are placed symmetrically with respect tothe memory element 32, as can be seen in part (3 a) of FIG. 14.

Yet another embodiment of the present invention is illustrated in parts(4 a) and (4 b) of the present invention, which are a top view and avertical cross-sectional view of a device according to this embodiment,respectively. Vertical asymmetrical return lines and horizontalasymmetrical return lines are provided, i.e. a column return line 35 isprovided for each column line 34 and associated therewith and a rowreturn line 80 is provided for each row line 33 an associated therewith.A column line 34 and its associated column return line 35 are placedasymmetrically with respect to the memory element 32, as can be seen inpart (4 b) of FIG. 14, i.e. there is an offset between column line 34and memory element 32 in the direction in which the row lines 33 extendand between return line 35 and memory element 32 in the direction inwhich the row lines 33 extend. In this embodiment, also a row line 33and its associated row return line 80 are placed asymmetrically withrespect to the memory element 32, as can be seen in part (4 a) of FIG.14, i.e. there is an offset between row line 33 and memory element 32 inthe direction in which the column lines 34 extend and between row returnline 80 and memory element 32 in the direction in which the column lines34 extend.

The influence on the cell size is represented by the rectangular boxes90 in FIG. 14, which represent a unit cell. The results are as follows:embodiments of FIG. 14, 1 a and 2 a have a cell size of 6F², theembodiment of FIG. 14, 3 a has a cell size of 10F² and the embodiment ofFIG. 14, 4 a has a cell size of 15F².

With respect to cross-talk reduction, two methods can be implementedaccording to the present invention: in first instance double symmetricalreturn lines in combination with extra currents through neighboringlines, or in second instance use of wider symmetrical or asymmetricalreturn lines. The first method requires 50% extra power consumption,whereas the second way requires ˜100% extra space. In the latter case,the cross-talk is reduced from 40% to 27% and 22% for symmetrical orasymmetrical return lines respectively, without loss of peak magneticfield.

It is to be understood that although preferred embodiments, specificconstructions and configurations, as well as materials, have beendiscussed herein for devices according to the present invention, variouschanges or modifications in form and detail may be made withoutdeparting from the scope and spirit of this invention. For example, theabove concept, although illustrated for 0T-1MTJ MRAM devices, can beimplemented in 1T-1MTJ or other MRAM structures.

1. A matrix with magnetoresistive memory cells logically organized inrows and columns, each memory cell including a magnetoresistive element,the matrix comprising a set of column lines, a column line being acontinuous conductive strip which is magnetically coupled to themagnetoresistive element of each of the memory cells of a column,wherein for each column line, at least one return column line isprovided for forming a return path for current in that column line andfor adding to a magnetic field influencing a selected magnetoresistiveelement and generated by current flow in the column line for increasingthe magnetic field for writing to the selected magnetoresistive element.2. A matrix according to claim 1, further comprising a set of row lines,a row line being a continuous conductive strip which is magneticallycoupled to the magnetoresistive element of each of the memory cells of arow.
 3. A matrix according to claim 1, wherein a return column line isthe same as a further column line.
 4. A matrix according to claim 1wherein the return column lines are different from the column lines. 5.A matrix according to claim 4, wherein for each column line a returncolumn line is provided at opposite sides of a column ofmagnetoresistive elements.
 6. A matrix according to claim 4, wherein thecolumn of magnetoresistive elements is placed offset in a row-directionwith regard to the center of the column lines.
 7. A matrix according toclaim 4, wherein the column of magnetoresistive elements is placedoffset in a row-direction with regard to the center of the return columnlines.
 8. A matrix according to claim 4, wherein the column ofmagnetoresistive elements is placed symmetrically with regard to boththe column line and at least one return column line.
 9. A matrixaccording to claim 2, wherein for each row line, at least one return rowline is provided for forming a return path for current in that row lineand for adding to the magnetic field of a selected magnetoresistiveelement.
 10. A matrix according to claim 1, wherein the column lines orthe return column lines are provided with a flux guiding cladding layer.11. A matrix according to claim 2, wherein the row lines are providedwith a flux guiding cladding layer.
 12. A matrix according to claim 9,wherein the return row lines are provided with a flux guiding claddinglayer.
 13. A nonvolatile memory comprising a matrix withmagnetoresistive memory cells according to claim
 1. 14. A method ofwriting a magnetoresistive element in a matrix of magnetoresistivememory elements arranged in logically organized rows and columns,comprising: combining, in the magnetoresistive element, a magnetic fieldfrom a current line with a magnetic field from at least one returncurrent line to thereby increase the magnetic field for writing to themagnetoresistive element.